1. Field of the Invention
The present invention relates to a semiconductor device having a multilevel metallization, and more particularly to a multilevel metallization structure thereof.
2. Description of the Related Art
There has been employed in recent years a multilevel metallization technology adapted for enhancing high integration of a semiconductor integrated circuit such as an IC, an LSI, etc.
A multilevel metallization structure formed on a conventional dielectric isolation substrate is disclosed, for example, in Japanese Patent Laid-Open Publication No. 57-45242. The isolation insulating film region on the dielectric isolation substrate is inevitably recessed in a fabrication process, as described later in detail. In the multilevel metallization structure, a lower metallization is frequently formed adjacent to the isolation insulating film region. Accordingly, there is formed a step height of which is the sum of the depth of the recess and the thickness of the lower metallization. In the multilevel metallization structure formed on the conventional dielectric isolation substrate, an upper metallization made of e.g. aluminum is formed so as to cross the step. Accordingly, there occurred such a problem that the upper metallization is broken at the step. Since the upper metallization is likely to be formed thin at the end of the step, there was such a problem that the lower metallization was broken as the time elapsed because of an electromigration which caused by the increase of the density of current at the end of the step in case the upper metallization was made of aluminum.